DMU - DMA Unit
Supports DMA transfers between M_CAN Message RAM and System Memory
Application & Technical Summary
The DMU signals to the attached DMA Controller (DMA request) when there is a newly received message available at one of the attached M_CAN's Rx FIFOs respectively when there is the possibility to load a new Tx message into the M_CAN's Tx FIFO/Queue.
The DMA controller then autonomously transfers the received message from the M_CAN's Message RAM to the System Memory or the message to be transmitted from the System Memory to the M_CAN's Message RAM.
After the DMA transfer has completed, the DMU acknowledges this to the M_CAN's Rx FIFO respectively sets the related M_CAN's transmission request.
Product benefits
- Allows to offload tasks from CPU to DMA controller by enabling DMA block transfers of M_CAN Rx/Tx FIFO elements between Message RAM and System Memory as well as the transfer of timestamps from optional TSU.
- Available for integration into microcontrollers, ASICs, and FPGAs.
up to 64 byte data transfer
in CAN FD frames
DMA unit for ASIC Design
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DMU
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Deliverables
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DMA unit for FPGA Design
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Intel / Altera
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AMD / Xilinx
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Deliverables
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DMU details
